Implementación de softcore RISC-V en FPGA

Abstract

This final integrative project consists of the development of a softcore that implements the RISC-V instruction set (ISA) in an FPCA. The softcore implementation is based on a pipeline type architecture and the complete system contains support for devices, interrupts, DRAM memory and interconnection to an AMBA bus, AXI4. Two of the peripherals implemented are an Ethernet MAC and a 16550 UART based on a Xilins IP core for each. The platform is capable of running Zephyr, an RTOS (Real Time Operating System), for which a driver that handles the Ethernet MAC was implemented, and through this, it is capable of connecting to an IPv4 network, requesting an IP address and run a Telnet server on it. The work carried out in this project includes the implementation of an automated continuous integration system, for the execution of the necessary steps for the compilation, synthesis, implementation and verification of the development.