Implementación en hardware de una arquitectura híbrida NTT y FFT, para algoritmos de criptografía post-cuántica y procesamiento de señales

Abstract

In this project, a hybrid RTL design was implemented and evaluated to compute the Fast Fourier Transform (FFT) and the Number Theoretic Transform (NTT), leveraging their strong architectural similarity. Different schemes for hardware acceleration of the Number Theoretic Transform (NTT) using lattice-based post-quantum encryption (PQC) algorithms were analyzed using FPGAs. By implementing both the NTT and the FFT in a single module, the hardware can be reused for signal processing whenever the NTT accelerator is not in use. Parameterized Verilog code was implemented to evaluate latencies and FPGA resource usage under different parallelization scenarios.